This is a follow-up to my article “Advanced VHDL verification on a budget”. This article is about understanding libraries in ModelSim, and how to tweak their location and visibility. Continue reading →

For many, advanced verification is synonymous to using SVA (SystemVerilog Assertions) and UVM (Universal Verification Methodology). Unfortunately, simulation tools supporting SVA are very expensive and quite out of reach for most FPGA developers. For developers using VHDL as their design language, it would also mean having to learn yet another language. Fortunately, low-cost VHDL alternatives exist. In fact, they may even be free. Continue reading →

Within an FPGA design team, developers may have many ideas on how data should be transferred between IP blocks. IP may be developed in-house, by consultants, by the FPGA vendors, or IP may be purchased from 3rd party vendors. Unfortunately, there is no single standard for interfacing between such IP, and a tremendous amount of time is generally being wasted by developers constantly inventing new interfaces, and by others trying to understand them and adapt to them.

In this article, I will explain the basics of how FPGA IP should be interconnected, and then suggest a standard that may be used by all FPGA designers for most designs. Continue reading →