Advanced VHDL verification on a budget

For many, advanced verification is synonymous to using SVA (SystemVerilog Assertions) and UVM (Universal Verification Methodology). Unfortunately, simulation tools supporting SVA are very expensive and quite out of reach for most FPGA developers. For developers using VHDL as their design language, it would also mean having to learn yet another language. Fortunately, low-cost VHDL alternatives exist. In fact, they may even be free.

Advanced VHDL verification for free

Advanced VHDL verification is based on using support libraries which add functionality and abstraction to the basic VHDL language. In the last few years several free alternatives have emerged, like:

I’m sure there are others. However – to support the advanced features of e.g. Bitvis UVVM, your simulator needs to support VHDL-2008, which is the latest addition (as per 2016) to the VHDL standard.

Finding a free simulator supporting VHDL-2008

Xilinx FPGA developers are most likely aware of the offerings from Xilinx, which is ISim (ISE Simulator) and Vivado Simulator. These are fantastic value, as they are free. Unfortunately, they do not support VHDL-2008.

Aldec Riviera Pro supports VHDL-2008. They have a free student edition, but they have no free alternatives for other users. I requested a free evaluation on their website, but I got a reply back that I wasn’t qualified and so I was rejected.

The de facto standard for FPGA simulation are the ModelSim and Questa simulator tools from Mentor Graphics. These are definitely not free, but for ModelSim there are special editions made available through the FPGA vendors. These limited editions are available for free:

ModelSim ME requires a license file from Microsemi (which is absolutely free), but it expires after one year and so has to be renewed. (I hate the idea of license files for free tools – what is the point of that?)

And the winner is: ModelSim Altera Starter Edition requires no license file. Just install and run – it couldn’t be any easier!

What about Xilinx users?

ModelSim ME and ModelSim Altera Edition both come with “precompiled libraries” for their respective technologies. You may think that you would not be able to use Xilinx specific libraries (UniSim, SimPrim, SecureIP) with these tools. Well, in fact you can. They just don’t tell you that. All you have to do is to compile these libraries yourself, in the same way you would with the full version of ModelSim or Questa. Here is the proof:

2016-03-21 12_37_22-ModelSim Microsemi 10.4c

Fig 1. Simulating Xilinx proprietary IP with ModelSim Microsemi edition

This is me simulating an example design included with Xilinx Vivado 2015.4, with a MIG DDR4 controller and with encrypted models of external DDR4 devices, using ModelSim ME. The exact same thing can be done with ModelSim Altera Starter Edition.

So – what’s the catch?

In addition to VHDL-2008 support, these free editions of ModelSim also have full Verilog support, and some limited support of SystemVerilog. Their limitation is the size of the project that you are able to simulate, and they may also limit your simulation speed.

This means that if you have a large FPGA design, you may not be able to run a top level testbench using the free editions. But if you limit your verification to module level simulation, the free ModelSim editions will serve you absolutely fine.

In my next post, I will describe a couple of tweaks to these simulators making them easier to use and to prepare them for my upcoming Bitvis UVVM tutorial.