Monthly Archives: July 2017

Tutorial: Create your own VVC for UVVM

VHDL designers are generally not spoiled with Verification IP (VIP). In fact, if you are using any sort of verification IP at all, then most likely it was developed in-house with the company you are working for. And most likely, such verification IP is a collection of BFM (Bus Functional Model) procedures which lacks any advanced features of a modern verification framework. Continue reading