Specifications

JanusHDL preview. What it does today, and what it does not do yet.

Language

VHDL	IEEE 1076-1993, 2002, 2008 and 2019. Choose with --std 93|02|08|19 (default 2008).
PSL	IEEE 1850 assertions in VHDL-2008 and 2019, and in -- psl comments with --psl.
Conditional analysis	VHDL-2019 `if directives, with your own identifiers given by -DNAME=VALUE.
Standard libraries	std and ieee built in: std_logic_1164, numeric_std, numeric_bit, the unsigned variants, math_real, math_complex, the fixed- and floating-point packages, std.env, std.reflection.
Verilog / SystemVerilog	Coming next.

Verification libraries

UVVM, OSVVM and VUnit testbenches run from their own sources, which you install yourself (see the UVVM tutorial). This preview does not bundle them: you choose the version your project uses.

Simulation

Engine	An interpreter that is the exact reference, and native code generation (--jit on) for the code that runs most. Both give the same results, message for message.
Process order	Deterministic: the order of processes within a simulation cycle is a fixed permutation (--order-seed N), so a race between processes shows up as a different result for another seed.
Recording	Every signal, into JanusHDL's waveform database (--wave, readable while it is written) or a VCD file (--vcd).
Analysis cache	--cache FILE keeps the analysis of a project and reuses it when no source file changed.
Limits	--max-memory (default 4 GB), --stop-time, and severity levels that stop the run or set the exit code.

Programs

jhdl	The command line: analyze, elaborate and run (jhdl --help).
jhdlw	The window: design hierarchy, waveforms of every VHDL type (records and arrays by field, enumerations, fixed and floating point and more radixes), simulation runs with their transcript (pause, run for a time, restart), panels to arrange, six themes.
jhdl-lsp	The language server, started by your editor.

Command-line front ends

Each compat/<family> folder holds small programs named like the commands of other simulators. Put one folder on your path and existing scripts run on JanusHDL; nothing else on your path changes.

Folder	Commands	Status
compat/vsim	vlib vmap vcom vopt vsim vdel, -do scripts	VHDL; a subset of the script commands
compat/xsim	xvhdl xelab xsim, -prj files, -tclbatch	VHDL; a subset of the script commands
compat/ghdl	ghdl -a -e -r --elab-run	VHDL
compat/nvc	nvc -a -e -r	VHDL
compat/asim, xrun, vcs	their commands	Not yet: they say so
compat/iverilog, verilator	their commands	With Verilog

Platforms

Windows	Windows 10 and 11, x86-64. One zip, nothing to install.
Linux	x86-64, glibc 2.28 or later: RHEL 8 and 9, Ubuntu 20.04 and later, Debian 10 and later. One tar.gz.
Linux ARM64	64-bit ARM, glibc 2.28 or later; tested on a Raspberry Pi 5 with Raspberry Pi OS (64-bit). One tar.gz.
Graphics	The window uses the GPU (DirectX 12 on Windows, Vulkan or OpenGL on Linux) and falls back to software rendering where there is none.