Welcome

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JanusHDL is an HDL simulator with a graphical workbench. It analyzes, elaborates and runs VHDL designs and their testbenches, from VHDL-1993 to VHDL-2019, with PSL, and it shows what happened: every signal's waveform, and why a signal has the value it has. Verilog and SystemVerilog come next.

JanusHDL is free of charge, for anyone and for any use, commercial work included. You may share unchanged copies of the download: with colleagues, on a shared drive, or in a CI image.

This manual is for FPGA and ASIC engineers who write VHDL and run testbenches, with UVVM, OSVVM, VUnit or a setup of their own, on Windows or Linux. It assumes you know VHDL and simulation; it does not assume you know JanusHDL.

What is in the download

One download holds three programs and a set of small front ends:

There is nothing else to install: the standard packages (std, and ieee from IEEE's official sources) are built in, and so are the legacy arithmetic packages that many designs still use. Verification libraries such as UVVM, OSVVM and VUnit are not part of the download; you get them from their own projects and analyze their sources with your design, as Libraries shows.

What JanusHDL does

• Runs VHDL from source. One command analyzes your files in order, elaborates the top level and runs it. Reports and failed assertions print with their time, delta cycle and source location, and the exit code tells a script whether the run passed.
• Checks against the standard. Every analysis message names its rule and the section of the IEEE 1076 standard (the LRM) it comes from, and says how to fix the code. Code that the standard forbids but whose meaning is clear can still be run, in compatibility mode.
• Gives the same result every time. The same design and inputs produce the same output on every run and every machine. You can also run the processes of each simulation cycle in another fixed order, to find testbenches that pass only by luck.
• Records everything. A run can record every signal into a waveform database, written as the simulation runs. The database also holds the design's structure (which processes drive and read each signal, and where in the source) and the delta cycles of every time step.
• Shows waveforms of any size. The viewer reads a recording a block at a time, as the screen needs it. A recording of 1.8 billion value changes (a 5.2 GB file) opened in under 4 seconds, in less than 1 GB of memory (measured).
• Explains values. Click a signal at a point in time and the Why this value? panel shows the processes that drive it, the signals they read and which of those changed last. Follow an X back to where it came from, step by step.
• Edits code. The window has a code editor with the analyzer's errors and warnings as you type, find and replace, folding and several cursors.
• Keeps a design together. A project file holds the sources with their libraries and VHDL versions, the top level, generics, stop time and options, in a text file made for version control.

Platforms

The programs are the same on every platform, and so are their results. Installing covers each.

JanusHDL is a preview

The current builds are previews. They are complete enough for real testbenches, and they are still changing: options, file formats and the window may change between versions. Project files and wave setup files carry a version number, so a newer build reads what an older one wrote, and a build tells you when a file is newer than it understands. Where something is not supported yet, JanusHDL says so in the message, by name, rather than failing silently. Troubleshooting and known limits lists what is missing today.

How this manual is organized

Conventions

• Monospace marks commands, options, file names and VHDL code. Words in capitals in a command, such as FILE.vhd or NAME, stand for what you fill in.
• Bold marks the names of menus, buttons, tabs and other parts of the window. File → Open project… means the Open project… item of the File menu.
• Keys are written as you press them: Ctrl+Shift+P means holding Ctrl and Shift while pressing P.
• Command examples are written for a Linux shell (or Git Bash on Windows); a single jhdl command works unchanged in PowerShell too. Where Windows needs something different, a PowerShell example follows. Paths use forward slashes, which JanusHDL accepts on Windows too.