JanusHDL

Insight panels

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A waveform shows what happened. The insight panels show why: which processes drive a signal, what those processes read, which of their inputs changed last, and in which delta cycle each change came. Following an unknown value back to where it came from takes a few clicks instead of a search through the source.

There are three panels, each a tab:

Panel Opens with Shows
Why this value? Signals → Why this value? The selected signal's value at the cursor, its drivers, and what each driver reads
Dataflow Signals → Show the dataflow and schematic of the selected signal The selected signal between the processes that drive and read it, as a graph; and a schematic of its instance
Delta cycles Signals → Show the delta cycles of the time step at the cursor The time step at the cursor, delta cycle by delta cycle

The commands are in the command palette too (Ctrl+Shift+P, then type why, dataflow or delta). The panels open beside the Terminal; like any tab, they can be moved, split beside the waves or put in a window of their own (Arranging the tabs).

What the panels need

The panels follow the wave view: the selected signal (click its name) and the cursor (click in the waves). As you select another signal or move the cursor, they update.

They read the design's structure and delta cycles from the recording. A simulation run in the window, and a waveform database written by jhdl --wave, have them: every process with its kind and place in the source, the signals each drives (with the lines that assign them) and the signals each reads, and the delta cycles of every time step. A VCD file holds values only, and so does a recording made by an earlier version of JanusHDL: the panels say so. A recording made with --wave-deltas off has the structure but no delta cycles: the Delta cycles panel says so, the others work.

Why this value?

Select a signal, place the cursor, and the panel shows:

  • The value at the cursor, since when the signal has it (with the delta cycle of that change), and the time of the cursor. Unknown values (U, X, W, -) show in red on a tint.
  • Driven by: the processes that drive the signal. A resolved signal with several drivers says so, Driven by 2 processes (resolved), and lists each: an X on a resolved signal often means two drivers drive it at once.
  • For each driver: its path in the design, its kind (process, concurrent assignment, concurrent assertion, concurrent procedure call, port connection, port default, PSL directive), a link to its place in the source, and the lines where it assigns the signal (assigns it at).
  • What each driver reads: every signal the process reads, with its value at the cursor and since when. The input that changed last is marked changed last: of what the process reads, it is the likeliest cause of the value. Hover over an input to see its full path, and whether it wakes the process (is in its sensitivity).

A signal that no process drives has the value it was declared with, is an input of the top level, or has a value forced on it; the panel says so. A driver that reads no signal gets its value from the process itself (a constant, a variable, a file).

Following a value back

Click an input to ask why it has its value: the panel moves to that signal, at the same cursor time. Following the inputs that are unknown and changed last walks an X back, process by process, to where it came from: an uninitialized register, a missing reset, two drivers fighting, a port left open.

The path you walked is shown at the top, rst_n ‹ ready ‹ data_valid; click an earlier name to go back to it, or press Back for one step.

  • The + button beside a signal shows it in the waves: it is added if it is not there, and selected.
  • A source link, such as uart_rx.vhd:112, opens the file at that line in the code editor.

Dataflow and schematic

Dataflow draws the selected signal in the middle; on the left, the processes that drive it, with the signals they read; on the right, the processes that read it, with the signals they drive. Each signal carries its value at the cursor, unknown values in red.

  • Click a signal to put it in the middle. Click a process to put it in the middle: it shows what it reads and what it drives, and the processes beyond.
  • Double-click a signal to show it in the waves, or a process to open its source in the editor.
  • Back returns to what was in the middle before.
  • Drag, or use the wheel, to pan; Ctrl+wheel or a pinch to zoom; Fit, or a double click on the background, shows all of it.
  • Hover over a signal or process for its full path and value.

Schematic (the button beside Dataflow) shows the instance of what is in the middle: its processes in columns in the direction values flow, each after those it reads from; the signals between them as labelled wires with their values; and the signals from and to the rest of the design as ports on the left and right. Large instances are drawn up to a limit, and the panel says how many processes were left out.

Delta cycles

Within one time step, a VHDL simulation runs any number of delta cycles: signal updates, then the processes they wake, whose assignments take effect in the next delta cycle. The waves draw each time step's last value; the Delta cycles panel shows the steps in between.

Place the cursor, and the panel shows the time step at the cursor (or the last one before it, and says so), delta cycle by delta cycle:

  • Each delta cycle: Delta 0, Delta 1 and so on (at time 0, Initialization first), with how many signals changed and how many processes ran.
  • The signals that changed in it, each from its old value to its new one, 0 → 1.
  • The processes that ran in it, with links to their source.

Click a signal to select it in the waves (it is added if it is not shown). The arrows at the top move the cursor to the time step before or after.

A signal that changes and changes back within one time step, a glitch of zero width, shows both changes here, though the wave, which draws only the step's last value, shows neither. This is also the place to see the order of events behind a race between processes (Determinism and races).

Messages carry their delta cycle too: 115 ns (delta 2) in the terminal is the delta cycle that this panel numbers 2.